The present invention generally relates to semiconductor manufacturing techniques which utilize deuterium passivation.
Semiconductor manufacturing has moved towards the production of smaller and smaller devices. As device dimensions continue to shrink, hot electrons play an increasing role in degrading device performance. This decrease in device performance is attributable to hot electrons pulling away hydrogen from the silicon lattice and creating unwanted interface states.
To attempt to increase device performance, some processes employ a late-stage hydrogenation procedure in which the device is hydrogenated near the end of processing to introduce/reintroduce hydrogen atoms to the polysilicon grain boundaries and to the Sixe2x80x94SiO2 interface. Some conventional processes perform late stage hydrogenation by heating a completed device to 400xc2x0 C., and exposing the device to hydrogen, with or without plasma. In these processes, the hydrogen diffuses through the device layers and eventually reaches the polysilicon gate dielectric interface to provide passivation. A problem with this approach is that the hydrogenation step is extremely slow or not possible due to impermeable barriers, taking in some instances more than ten hours to perform per substrate. Thus, improved device performance comes at the expense of reduced process throughput. In addition, the hydrogen annealing typically does not passivate 100% of the defects.
U.S. Pat. No. 5,711,998 to Shufflebotham describes a method of hydrogenating a polycrystalline silicon in an electrical device including the step of placing a substrate having a polysilicon component in a radio frequency induced low-pressure, high-density plasma reactor. The method further includes introducing a gas including at least hydrogen or deuterium into the reactor. Hydrogenation of the polysilicon component is accomplished by striking a plasma in the RF induced low pressure, high-density plasma reactor under conditions that promote hydrogenation of the polysilicon component.
U.S. Pat. No. 5,830,575 to Warren discloses a memory device that is constructed as a silicon-silicon dioxide-silicon layered structure. Protons are introduced laterally into the structure through the exposed edges of the silicon dioxide layer during a high temperature anneal in an atmosphere containing hydrogen gas.
U.S. Pat. No. 5,250,446 to Osawa et al. describes a process where a semiconductor substrate is exposed to a mixture of charged particles including hydrogen ions, deuterium ions, and molecular hydrogen and deuterium. Due to differences in mass, the deuterium ions are introduced into the substrate at a different depth than the hydrogen ions.
Passivating with deuterium, as compared to hydrogen, produces improved long term hot electron resistance. The excitation lifetime of deuterium is lower than hydrogen; therefore, the chance of being bombarded by a second electron while excited and escaping from the silicon lattice is significantly less for deuterium. However, a deuterium anneal performed at the beginning of a manufacturing process to deuterate a gate oxide/silicon interface may not provide the performance characteristics desired.
This is because subsequent processing steps can degrade deuterium levels. Therefore, it would be beneficial to provide a process which allows the deuterium to remain in the device after all processing is complete.
It is an object of the invention to provide semiconductor substrates with deuterium ingress paths closely positioned to semiconductor devices which allow passivation to be easily performed towards the end of processing.
It is another object of the invention to provide methods for producing semiconductor substrates with deuterium reservoirs closely positioned to semiconductor devices.
It is another object of the invention to provide methods for annealing to be performed at the end of the manufacturing process so as to allow optimum deuterium levels to be obtained.
It is another object of the invention to provide structures of deuterium reservoirs in semiconductor devices for deuterium passivation during semiconductor manufacturing.
It is another object of the invention to provide an ingress path through a barrier layer to allow deuterium to enter into the gate region of a device and then to cap that ingress path so as to avoid ionic contamination.
It is yet another object of the invention to provide a deuterium ingress path through a back of the semiconductor wafer by providing trenches in the semiconductor from the front filled with a material through which deuterium can diffuse and backside grinding or polishing to expose the base of one or more of these regions from the back.
According to one embodiment of the invention, deuterium reservoir plugs are formed in a semiconductor structure and serve as a source of deuterium for passivating semiconductor devices within the semiconductor structure. The semiconductor structure includes a substrate in which one or more semiconductor devices are formed.
A barrier layer is applied over the substrate and is overcoated with an insulator material. The barrier layer is made from a material which prevents or resists deuterium diffusion therethrough. Silicon nitride is an example of a suitable barrier material. The insulator material and portions of the barrier layer are then patterned to create one or more trenches which extend from the surface of the insulator material to the semiconductor device. In one aspect of this embodiment, at least one trench is filled with a deuterated material which will serve as a reservoir for deuterium to passivate the device. Additional trenches may be filled with electrically conductive material, and these trenches may extend through the barrier layer, or to circuitry positioned above the barrier layer. In a preferred embodiment, the trench is filled with deuterated silicon nitride; however, deuterated metal hydrides and deuterated refractory metals could be used (e.g., CVD tungsten based materials, such as tungsten, tungsten silicide or tungsten nitride; and similar CVD tantalum or titanium based materials). In general, group 4b and 5b elements or alloys (e.g., PdxAg1-x) including Ti, Zr, Hf, V, Nb, Ta, Ni, Cr, Cu, Pd, Y (transition metals) and Eu form hydrides and have high hydrogen/deuterium solubility. In addition, deuterated amorphous silicon, amorphous or polycrystalline carbon, amorphous SiC, amorphous SiGe, SiO2, Si3N4, phosphorus and/or boron doped SiO2 can act as deuterium reservoirs. In another aspect of this embodiment, at least one trench is lined with a deuterated material which will serve as a reservoir for deuterium to passivate the device. The remainder of the trench is then filled with an electrically conductive material such as tungsten, titanium lined tungsten, tantalum lined copper, or titanium lined aluminum-copper. Towards the end of manufacturing, the semiconductor structure can be placed in an oven and annealed at a temperature sufficient to cause the deuterium in the deuterium reservoirs to diffuse throughout the structure at sections not blocked by the barrier layer. A suitable anneal temperature will should range from 300xc2x0 C. to 800xc2x0 C., with 400xc2x0 C. being optimal, and the anneal time will be generally greater than one minute (e.g., approximately thirty minutes). The time and temperature will vary depending on the characteristics of the semiconductor structure.
According to a second embodiment of the invention, one or more ingress paths are formed through a barrier to permit deuterium diffusion to gate dielectric. The ingress path is then capped with an ion barrier. The ingress paths can be through thin films on the front surface of the wafer or through the silicon from the back. To provide the latter, isolation regions, such as shallow trench isolations, are formed in a semiconductor substrate which includes semiconductor devices and/or circuitry formed on a top surface. The back side of the semiconductor substrate is subjected to grinding and/or polishing or equivalent treatments to remove portions of the substrate in order to expose the bottom of the isolation regions. The isolation regions are adjacent to and connected with semiconductor devices through a deuterium diffusion path, such as SiO2, formed in the semiconductor substrate, and serve as deuterium ingress pathways after the grinding or polishing is performed. Specifically, after grinding or polishing, the bottom of the isolation region is exposed from the back side. Because the isolation region is filled with a material which permits deuterium diffusion therethrough, an anneal in the presence of deuterium gas or deuterium plasma will allow deuterium to diffuse through the back of the isolation regions up to the semiconductor devices formed at the top of the semiconductor substrate. Alternative mechanisms, such as exposure to photon sources including lasers and microwaves, could also be used to enhance deuterium diffusion through the ingress pathways.